1. Field of the Invention
The present invention relates to an operating method of a memory device. More particularly, the present invention relates to an operating method of a non-volatile memory device.
2. Description of Related Art
Non-volatile memory (NVM) is a semiconductor memory which can continue to store data after power is turned off. NVM includes mask read-only memory (Mask ROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), and flash memory. NVM has been broadly applied in semiconductor industry and is a memory researched and developed for preventing program data loss. Generally, NVM can be programmed, read, and/or erased based on the eventual application requirement of a device and can store program data for long time.
Flash memory generally includes a memory cell array arranged in columns and rows. Each memory cell includes a MOS transistor having a gate, a drain, a source, and a channel between the drain and the source. The gate corresponds to a word line, and the drain/source correspond to bit lines of the memory array. Presently the gate of flash memory is usually double gate structure including a gate and a floating gate, wherein the floating gate is disposed between two dielectric layers for trapping carriers such as electrons, so as to “program” the memory cell. In other words, in conventional memory cell, the tunneling oxidation layer is disposed on the channel, the floating gate is disposed on the tunneling oxidation layer, the inter-gate dielectric layer is disposed on the floating gate, and the gate is disposed on the inter-gate dielectric layer.
When programming is performed, a set of programming biases are supplied to the selected word line and bit line. Biases are supplied to one or multiple memory cells corresponding to the selected word line and bit line in programming state. As to a single memory cell, different biases are supplied to the source and the drain thereof so that electric field is formed along the channel thereof, accordingly electrons gain enough power to tunnel the first dielectric layer to enter the floating gate and to be stored therein. Electrons are stored in the floating gate and accordingly the threshold voltage of the memory cell is changed, thus, whether the memory cell has been programmed can be known from the change of the threshold voltage thereof.
Read bias is supplied to a memory cell to read the memory cell, and the current passing through the memory cell is read by a sensing component. If the memory cell is programmed or electrons are stored in the floating gate thereof, then the quantity of the current thereof is different from the currents of those unprogrammed memory cells. Accordingly, the state of each memory cell can be obtained by the sensing component through the quantity of the current of the memory cell.
To erase information in a flash memory cell, erase bias has to be supplied to the memory cell to force electrons stored in the floating gate of the memory cell to tunnel out of the floating gate of the memory cell by known mechanism such as Fowler-Nordheim (FN) tunneling.
In a present NVM, the tunneling oxidation layer is disposed on the channel so that the bird beak effect caused by shallow trench isolation structure affects the tunneling oxidation layer severely, thus, the device cannot be minimized. On the other hand, high voltage is required by the electron tunneling programming or erasing operation of the present NVM, thus, the power consumption of the device is high, and the speed of performing the operations needs to be improved.
Accordingly, an operating method of memory cell which can resolve the aforementioned problems is required in memory cell design and in the technology of memory cell array devices.